1. Field of the Invention
The present invention generally relate to simulation methods and computer-readable storage media, and more particularly to a simulation method for analyzing a semiconductor integrated circuit and to a computer-readable storage medium which stores a program for causing a computer to carry out procedures of such a simulation method.
2. Description of the Related Art
Conventionally, when carrying out a timing analysis or simulation of a circuit in at a layout design stage, for example, a net list is used. This net list includes information related to the types of cells or elements forming the circuit, dimensions of each part of the element and the like. However, the size of semiconductor integrated circuits, such as Large Scale Integrated (LSI) circuits, has become extremely small, and recently, it has become impossible to sufficiently describe the characteristics of the circuit using only the information included in the net list. For example, even the cells or circuits having the same shape may have different circuit characteristics depending on the layout patterns and the layout positions. The main reasons for the different circuit characteristics depending on the layout patterns and the layout positions include deviations in the circuit characteristics dependent on a pitch of polysilicon gates of transistors and deviations in the circuit characteristics dependent on stress caused by Shallow Trench Isolation (STI). Such deviations in the circuit characteristics have become more notable as the size of the LSI circuits has become smaller, and the effects of the deviation in the circuit characteristics on the timing analysis is becoming more and more complex.
A following method is known for carrying out a simulation of a circuit. The method carries out a simulation of a circuit based on the net list and parameters that are obtained from actually measured data of device characteristics.
The conventional timing analysis of the circuit is based on the net list which does not take into consideration the layout patterns and the layout positions of the circuit. For this reason, it is impossible to take into consideration the deviation in the circuit characteristic that occurs as the size of the LSI circuits is further reduced, and it is difficult to further improve the accuracy of the timing analysis.